The present invention relates generally to integrated circuit devices, and more specifically to integrated circuit devices which have no device pin assigned to the test mode function.
Stress testing is a critical step in the manufacture of an integrated circuit device. Stress testing provides important information on the reliability of the device and may indicate latent manufacturing and design problems which may then be remedied before the device is actually sold to a customer. Stress testing of an integrated circuit device is often performed during the burn-in phase of device manufacture when a test mode of the device is entered and the device is subjected to various stress tests well known in the art.
Often the testing of an integrated circuit device becomes complicated when no device pin is dedicated to the test mode function. This often occurs in high performance parts where every pin of the device is dedicated to functions, other than testing, which are necessary to the normal operation of the device. The very fast Burst Random Access Memory (RAM) device is an example of a high performance integrated circuit device which has no pins dedicated to entering a test mode.
The very fast Burst RAM device is a synchronous SRAM device which has a burst mode and is therefore used as an integral component in cache memory systems, often as a burstable, high performance secondary cache for microprocessors such as the Intel 486 or the Motorola family of microprocessors. SGS-Thomson Microelectronics, Inc. manufactures the M62486(Q) for use with the Intel i486 family of microprocessors and the M62940A for use with the Motorola MCM62940 family of microprocessors. The M62940A device produces a burst of data in a straight binary count (00, 01, 10, 11, etc.) as needed by the Motorola microprocessor, while the M62486(Q) device produces a more complicated burst of data which may count forwards or backwards in a binary count as a function of the initial state of the least significant address bit. Thus, the very fast Burst RAM device of either type has a burst counter which controls the burst mode, and the type of count provided by the burst counter to the microprocessor is a function of the type of count required by the microprocessor, as described above.
The very fast Burst RAM device uses a reserved pin (RES bar) to select the burst count desired. Typically, the reserved pin is tied to a low logic level, Gnd, for the Intel compatible M62486R(Q) device and is tied to a high logic level, Vcc, for the Motorola compatible M62940A device. With the reserved pin thus committed to the function of defining the type burst count the very fast Burst RAM will produce, the reserved pin is not readily available to help define the test mode of the device. Initially, the test mode for the Burst RAM was entered by applying a negative super voltage on the reserved pin signal (RES bar) and appropriately applying power supply voltages Vcc and Vss to two address pins in order to define the desired test mode. However, this approach was too complicated for the burn-in ovens to handle. Thus, there exists a current need in the art to be able to utilize an integrated device pin already committed to a normal operation function to a test mode function so that the device may be entered into a test mode for stress testing during burn-in of the device.
Another concern with stress testing of integrated circuit devices, such as the very fast Burst RAM, is that adequate stressing of the device be accomplished such that acceptable levels of device reliability are achieved. The very fast Burst RAM device, for instance, is fully synchronous and has many internally self timed clocks. For both read and write cycles, the very fast Burst RAM device times out when the read or write operation is complete. While this time out feature ensures low power consumption, it does not stress the device throughout a memory cycle and thus does not allow for adequate stress testing of the device. A device will undergo burn-in testing during the production flow and, if the device is tested while the device times out, maximum stressing of the device is not obtained. Thus, is it important to not only be able to enter a device test mode, but to ensure that once a test mode is entered that the device is adequately tested.